A research paper co-authored by Professor Lim Se-Min of the SATA Lab at the College of Software Convergence at Kookmin University (President Jeong Seung Ryul), who served as the principal investigator, in collaboration with researchers from the University of California, Irvine (UC Irvine), has been accepted for presentation at ICCAD 2026, the world’s most prestigious academic conference in the field of semiconductor design automation (CAD). Titled “FMiner: CPU-FPGA Heterogeneous Framework for Frequent Itemset Mining and Beyond,” the paper addresses system design techniques in which CPUs and FPGAs efficiently divide and process complex data analysis tasks. ICCAD (International Conference on Computer-Aided Design) is an international academic conference jointly sponsored by the IEEE and ACM, and will be held in San Jose, California, from November 8 to 12.

“Frequent itemset mining,” the subject of this study, is a big data processing technique that identifies combinations of items that frequently appear together in large volumes of records. It is characterized by the need for both complex decision-making to eliminate unnecessary candidates and repetitive, large-scale computations. While assigning these two tasks to a CPU and an FPGA, respectively, allows for the utilization of each device’s strengths, the frequent data transfers and latency that occur between them limit overall performance. This study focused on reducing this communication burden to translate the benefits of task distribution into actual analytical performance.
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“FMiner,” developed by the research team, assigns the tasks of controlling the search and reducing unnecessary candidates to the CPU, while offloading the computation of comparing large volumes of records where each item appears to an FPGA—a reconfigurable semiconductor. The data exchanged between the two devices is maintained in a compressed format; it is decompressed only when calculated within the FPGA and then recompressed afterward. Furthermore, they reduced communication latency by grouping independent search tasks and transferring data for the next group while the current group was being processed.
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The research team built a prototype by integrating a single AMD/Xilinx Alveo U50 FPGA with a desktop-class computer and evaluated it using datasets of varying sizes and densities. Across the entire evaluation dataset, data intended for transmission was compressed to approximately one-fourth of its original size. In the cost analysis, the team assumed that the Borgelt implementation of the CPU-based Eclat software scales ideally across 48 cores and factored in the system’s purchase cost; based on this benchmark, FMiner’s price-performance ratio was found to be up to approximately 11 times higher. This result stems from designing the entire system—including data movement—to reduce communication overhead and enhance cost efficiency.
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Professor Lim Se-Min, the principal investigator of this study, stated, “To effectively leverage both the CPU’s complex search capabilities and the FPGA’s high computational throughput, we must also consider data movement and latency between the two devices.” He added, “This study is significant because it reduced communication overhead and improved the cost-efficiency of actual analysis by jointly designing the algorithm’s task distribution, data compression, and hardware architecture.” He continued, “We hope this design approach will serve as a foundation for effectively utilizing accelerator performance in various future data analysis systems and for conducting large-scale analyses more cost-effectively.”