Integrated System's Lab was awarded for excellence at the 18th Korean Conference on Semiconductors.
- 11.05.24 / 박채형
The Department of Electronic Engineering Integrated System's Lab (adviser, Min Kyung Sik) was awarded for excellence at the 18th Korean Conference on Semiconductors.
Kookmin University's Department of Electronic Engineering Integrated System's Lab (adviser, Min Kyung Sik) was awarded a CAD & Design Methodology Award and a Design Excellence Award in the Chip Design Contest at the 18th Korean Conference on Semiconductors.
Integrated System's Lab's team Joo Kwan Hee (Master's degree), Jung Chual Moon (Master's degree), Lee Eun Sup (Master's degree) was awarded a CAD & Design Methodology Award by suggesting a model of resistance memory which is expected as a next memory element's Verilog-A and a simulation method including an element's characteristic change according to PVT change through their thesis . For this, they developed a practicable Emulator with a CMOS process.
Also, Integrated System's Lab's Joo Kwan Hee (Master's degree student) was awarded for design excellence in the Chip Design Contest for his thesis. He developed a Zero-standby-power flip-flop circuit using a resistance memory which is expected to be the next memory element. The circuit doesn't spend standby and leak power during waiting time.
Integrated System's Lab was awarded for excellence at the 18th Korean Conference on Semiconductors. |
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2011-05-24
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Kookmin University's Department of Electronic Engineering Integrated System's Lab (adviser, Min Kyung Sik) was awarded a CAD & Design Methodology Award and a Design Excellence Award in the Chip Design Contest at the 18th Korean Conference on Semiconductors. Integrated System's Lab's team Joo Kwan Hee (Master's degree), Jung Chual Moon (Master's degree), Lee Eun Sup (Master's degree) was awarded a CAD & Design Methodology Award by suggesting a model of resistance memory which is expected as a next memory element's Verilog-A and a simulation method including an element's characteristic change according to PVT change through their thesis . For this, they developed a practicable Emulator with a CMOS process. Also, Integrated System's Lab's Joo Kwan Hee (Master's degree student) was awarded for design excellence in the Chip Design Contest for his thesis. He developed a Zero-standby-power flip-flop circuit using a resistance memory which is expected to be the next memory element. The circuit doesn't spend standby and leak power during waiting time. |